caution: these devices are sensitive to electrostatic discharge. users should follow proper i.c. handling procedures. copyright ? harris corporation 1993 december 1993 8-5 semiconductor ad7520, ad7530 ad7521, ad7531 10-bit, 12-bit multiplying d/a converters description the ad7520/ad7530 and ad7521/ad7531 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution, multiplying digital-to-analog converters (dac). harris' thin- ?lm on cmos processing gives up to 10-bit accuracy with ttl/cmos compatible operation. digital inputs are fully protected against static discharge by diodes to ground and positive supply. typical applications include digital/analog interfacing, multiplication and division, programmable power supplies, crt character generation, digitally controlled gain circuits, integrators and attenuators, etc. the ad7530 and ad7531 are identical to the ad7520 and ad7521, respectively, with the exception of output leakage current and feedthrough speci?cations. features ? ad7520/ad7530 10 bit resolution; 8, 9 and 10 bit linearity ? ad7521/ad7531 12 bit resolution; 8, 9 and 10 bit linearity ? low power dissipation of 20mw (max) ? low nonlinearity tempco at 2ppm of fsr/ o c ? current settling time 1.0 m s to 0.05% of fsr ? 5v to +15v supply voltage range ? ttl/cmos compatible ? full input static protection ? /883b processed versions available file number 3104 december 1993 ordering information part number nonlinearity temperature range package ad7520jn, ad7530jn 0.2% (8-bit) 0 o c to +70 o c 16 lead plastic dip ad7520kn, ad7530kn 0.1% (9-bit) 0 o c to +70 o c 16 lead plastic dip ad7521jn, ad7531jn 0.2% (8-bit) 0 o c to +70 o c 18 lead plastic dip ad7521kn, ad7531kn 0.1% (9-bit) 0 o c to +70 o c 18 lead plastic dip ad7520ln, ad7530ln 0.05% (10-bit) -40 o c to +85 o c 16 lead plastic dip ad7521ln, ad7531ln 0.05% (10-bit) -40 o c to +85 o c 18 lead plastic dip ad7520jd 0.2% (8-bit) -25 o c to +85 o c 16 lead ceramic dip ad7520kd 0.1% (9-bit) -25 o c to +85 o c 16 lead ceramic dip ad7520ld 0.05% (10-bit) -25 o c to +85 o c 16 lead ceramic dip ad7520sd, ad7520sd/883b 0.2% (8-bit) -55 o c to +125 o c 16 lead ceramic dip ad7520td 0.1% (9-bit) -55 o c to +125 o c 16 lead ceramic dip ad7520ud, ad7520ud/883b 0.05% (10-bit) -55 o c to +125 o c 16 lead ceramic dip pinouts ad7520, ad7530 (cdip, pdip) top view ad7521, ad7531 (pdip) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 i out1 i out2 gnd bit 1 (msb) bit 2 bit 3 bit 5 bit 4 r feedback v+ bit 10 (lsb) bit 9 bit 8 bit 7 bit 6 v ref i out1 i out2 gnd bit 1 (msb) bit 2 bit 3 bit 5 bit 4 r feedback v+ bit 11 bit 9 bit 8 bit 7 v ref 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 bit 12 (lsb) bit 10 bit 6
8-6 speci?cations ad7520, ad7530, ad7521, ad7531 absolute maximum ratings thermal information supply voltage (v+ to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . +17v v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . v+ to gnd output voltage compliance . . . . . . . . . . . . . . . . . . . . -100mv to v+ storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300 o c thermal resistance q ja q jc 16 lead plastic dip . . . . . . . . . . . . . . . . . 100 o c/w - 18 lead plastic dip . . . . . . . . . . . . . . . . . 90 o c/w - 16 lead ceramic dip . . . . . . . . . . . . . . . 80 o c/w 24 o c/w maximum power dissipation up to +75 o c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450mw derate above +75 o c at 6mw/ o c operating temperature jn, kn, ln versions . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c jd, kd, ld versions . . . . . . . . . . . . . . . . . . . . . . . -25 o c to +85 o c sd, td, ud versions. . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. the digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic ?elds. keep unused units in conductive foam at all times. do not apply voltages higher than v dd or less than gnd potential on any terminal except v ref and r feedback . electrical speci?cations v+ = +15v, v ref = +10v, t a = +25 o c unless otherwise speci?ed parameter test conditions ad7520/ad7530 ad7521/ad7531 units min typ max min typ max system performance (note 1) resolution 10 10 10 12 12 12 bits nonlinearity j, s s over -55 o c to +125 o c (notes 2, 5) (figure 2) -- 0.2 (8-bit) -- 0.2 (8-bit) % of fsr k, t t over -55 o c to +125 o c (figure 2) -- 0.1 (9-bit) -- 0.1 (9-bit) % of fsr l, u -10v v ref +10v u over -55 o c to +125 o c (figure 2) -- 0.05 (10-bit) -- 0.05 (10-bit) % of fsr nonlinearity tempco -10v v ref +10v (notes 2, 3) -- 2- - 2 ppm of fsr/ o c gain error - 0.3 - - 0.3 - % of fsr gain error tempco - - 10 - - 10 ppm of fsr/ o c output leakage current (either output) over the specified temperature range -- 200 ( 300) -- 200 ( 300) na dynamic characteristics output current settling time to 0.05% of fsr (all digital inputs low to high and high to low) (note 3) (figure 7) - 1.0 - - 1.0 - m s feedthrough error v ref = 20v p-p , 10khz (50khz) all digital inputs low (note 3) (figure 6) - - 10 - - 10 mv p-p reference input input resistance all digital inputs high i out1 at ground 5 10 20 5 10 20 k w analog output output capacitance i out1 all digital inputs high (note 3) (figure 5) - 200 - - 200 - pf i out2 -75 --75 - pf i out1 all digital inputs low (note 3) (figure 5) -75 --75 - pf i out2 - 200 - - 200 - pf
8-7 speci?cations ad7520, ad7530, ad7521, ad7531 functional diagram switches shown for digital inputs high. resistor values are typical. output noise both outputs (note 3) (figure 4) - equivalent to 10k w - - equivalent to 10k w - johnson noise digital inputs low state threshold, v il over the specified temperature range v in = 0v or +15v - - 0.8 - - 0.8 v high state threshold, v ih 2.4 - - 2.4 - - v input current, i il , i ih -- 1- - 1 m a input coding see tables 1 & 2 binary/offset binary power supply characteristics power supply rejection v+ = 14.5v to 15.5v (note 2) (figure 3) - 0.005 - - 0.005 - % fsr/% d v+ power supply voltage range +5 to +15 +5 to +15 v i+ all digital inputs at 0v or v+ excluding ladder network - 1-- 1- m a all digital inputs high or low excluding ladder network -- 2-- 2ma total power dissipation including the ladder network - 20 - - 20 - mw notes: 1. full scale range (fsr) is 10v for unipolar and 10v for bipolar modes. 2. using internal feedback resistor r feedback . 3. guaranteed by design, or characterization and not production tested. 4. accuracy not guaranteed unless outputs at gnd potential. 5. accuracy is tested and guaranteed at v+ = 15v only. electrical speci?cations v+ = +15v, v ref = +10v, t a = +25 o c unless otherwise speci?ed (continued) parameter test conditions ad7520/ad7530 ad7521/ad7531 units min typ max min typ max 20k w gnd i out2 i out1 r feedback bit 3 bit 2 msb v ref 20k w 20k w 20k w 20k w 20k w 10k w 10k w 10k w 10k w spdt nmos switches 10k w
8-8 ad7520, ad7530, ad7521, ad7531 pin descriptions ad7520/30 ad7521/31 pin name description 11i out1 current out summing junction of the r2r ladder network. 22i out2 current out virtual ground, return path for the r2r ladder network 3 3 gnd digital ground. ground potential for digital side of d/a. 4 4 bits 1(msb) most signi?cant digital data bit 5 5 bit 2 digital bit 2 6 6 bit 3 digital bit 3 7 7 bit 4 digital bit 4 8 8 bit 5 digital bit 5 9 9 bit 6 digital bit 6 10 10 bit 7 digital bit 7 11 11 bit 8 digital bit 8 12 12 bit 9 digital bit 9 13 13 bit 10 digital bit 10 (ad7521/31), least signi?cant digital data bit (ad7520/30) - 14 bit 11 digital bit 11 (ad7521/31) - 15 bit 12 least signi?cant digital data bit (ad7521/31) 14 16 v+ power supply +5 to +15 volts 15 17 v ref voltage reference input to set the output range. supplies the r2r resistor ladder. 16 18 r feedback feedback resistor used for the current to voltage conversion when using and external op-amp. de?nition of terms nonlinearity: error contributed by deviation of the dac transfer function from a best straight line through the actual plot of transfer function. normally expressed as a percent- age of full scale range or in (sub)multiples of 1 lsb. resolution: it is addressing the smallest distinct analog output change that a d/a converter can produce. it is commonly expressed as the number of converter bits. a converter with resolution of n bits can resolve output changes of 2 -n of the full-scale range, e.g. 2 -n v ref for a unipolar conversion. resolution by no means implies linearity. settling time: time required for the output of a dac to set- tle to within speci?ed error band around its ?nal value (e.g. 1/2 lsb) for a given digital input change, i.e. all digital inputs low to high and high to low. gain error: the difference between actual and ideal analog output values at full-scale range, i.e. all digital inputs at high state. it is expressed as a percentage of full-scale range or in (sub)multiples of 1 lsb. feedthrough error: error caused by capacitive coupling from v ref to i out1 with all digital inputs low. output capacitance: capacitance from i out1 , and i out2 terminals to ground. output leakage current: current which appears on i out1 , terminal when all digital inputs are low or on i out2 terminal when all digital inputs are high. detailed description the ad7520, ad7530, ad7521 and ad7531 are monolithic, multiplying d/a converters. a highly stable thin ?lm r-2r resistor ladder network and nmos spdt switches form the basis of the converter circuit, cmos level shifters permit low power ttl/cmos compatible operation. an external voltage or current reference and an operational ampli?er are all that is required for most voltage output applications. a simpli?ed equivalent circuit of the dac is shown in the func- tional diagram. the nmos spdt switches steer the ladder leg currents between i out1 and i out2 buses which must be held either at ground potential. this con?guration maintains a con- stant current in each ladder leg independent of the input code. converter errors are further reduced by using separate metal interconnections between the major bits and the out- puts. use of high threshold switches reduce offset (leakage) errors to a negligible level. the level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the ?rst, see figure 1. this con?guration results in ttl/cmos compatible operation over the full military temperature range. with the lad- der spdt switches driven by the level shifter, each switch is binarily weighted for an on resistance proportional to the respective ladder leg current. this assures a constant voltage drop across each switch, creating equipotential terminations for the 2r ladder resistors and highly accurate leg currents. figure 1. cmos switch v+ dtl/ttl/ cmos input 13 4 5 6 7 2 89 to ladder i out2 i out1
8-9 ad7520, ad7530, ad7521, ad7531 test circuits the following test circuits apply for the ad7520. similar circuits are used for the ad7530, ad7521 and ad7531. figure 2. nonlinearity figure 3. power supply rejection figure 4. noise figure 5. output capacitance figure 6. feedthrough error figure 7. output current settling time 10 bit binary counter gnd 15 16 1 5 4 13 32 ad7520 bit 1 (msb) bit 10 (lsb) linearity error x 100 r feedback i out1 i out2 ha2600 - + v ref bit 1 (lsb) bit 10 bit 11 bit 12 10k w 0.01% 1m w 10k w 0.01% clock +15v v ref ha2600 - + 12 bit reference dac 15 16 1 5 4 13 32 ad7520 bit 1 (msb) bit 10 (lsb) ha2600 - + ha2600 - + 500k w ungrounded sine wave generator 400hz 1.0v p-p 5k w 0.01% 5k 0.01% r feedback +15v +10v v ref i out1 i out2 14 gnd 15 2 5 4 13 3 1 ad7520 101aln - + 0.1 m f i out1 i out2 14 10k w v out 100 w 15 m f 1k +15v 50k w 1k w 50v f = 1khz bw = 1hz quan tech model 134d wave analyzer +11v (adjust for v out = 0v) 15 16 1 5 4 13 3 2 ad7520 bit 1 (msb) bit 10 (lsb) 14 +15v nc scope 100mv p-p 1mhz nc 1k w +15v 15 16 1 5 4 13 3 2 ad7520 bit 1 (msb) bit 10 (lsb) 14 +15v v ref = 20v p-p gnd i out1 i out2 2 3 6 v out 100khz sine wave ha2600 - + 15 1 5 4 13 3 2 ad7520 bit 1 (msb) bit 10 (lsb) 14 +15v scope +100mv 100 w gnd v ref digital i out2 extrapolate 5t: 1% settling (1mv) 8t: 0.03% settling t = rise time input +5v 0v -10v
8-10 ad7520, ad7530, ad7521, ad7531 applications unipolar binary operation the circuit con?guration for operating the ad7520 in unipo- lar mode is shown in figure 8. similar circuits can be used for ad7521, ad7530 and ad7531. with positive and nega- tive v ref values the circuit is capable of 2-quadrant multipli- cation. the digital input code/analog output value table for unipolar mode is given in table 1. figure 8. unipolar binary operation (2-quadrant multiplication zero offset adjustment 1. connect all digital inputs to gnd. 2. adjust the offset zero adjust trimpot of the output opera- tional ampli?er for 0v at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor vout for a -v ref (1-2 -n ) reading. (n = 10 for ad7520/30 and n = 12 for ad7521/31). 3. to decrease v out , connect a series resistor (0 to 250 w ) between the reference voltage and the v ref terminal. 4. to increase v out , connect a series resistor (0 to 250 w ) in the i out1 ampli?er feedback loop. bipolar (offset binary) operation the circuit con?guration for operating the ad7520 in the bipolar mode is given in figure 9. similar circuits can be used for ad7521, ad7530 and ad7531. using offset binary digital input codes and positive and negative reference volt- age values, 4-quadrant multiplication can be realized. the table 1. code table - unlpolar binary operation digital input analog output 1111111111 -v ref (1-2 -n ) 1000000001 -v ref ( 1 / 2 + 2 -n ) 1000000000 -v ref /2 0111111111 -v ref ( 1 / 2 -2 -n ) 0000000001 -v ref (2 -n ) 0000000000 0 notes: 1. lsb = 2 -n v ref 2. n = 10 for 7520, 7530 n = 12 for 7521, 7531 15 16 1 5 4 13 3 2 ad7520 bit 1 (msb) bit 10 (lsb) 14 +15v v ref gnd i out1 i out2 6 v out - + r feedback digital input digital input code/analog output value table for bipolar mode is given in table 2. figure 9. bipolar operation (4-quadrant multiplication) a logic 1 input at any digital input forces the corresponding ladder switch to steer the bit current to i out1 bus. a logic 0 input forces the bit current to i out2 bus. for any code the i out1 and i out2 bus currents are complements of one another. the current ampli?er at i out2 changes the polarity of i out2 current and the transconductance ampli?er at i out1 output sums the two currents. this con?guration doubles the output range. the difference current resulting at zero offset binary code, (msb = logic 1, all other bits = logic 0), is corrected by using an external resistor, (10m w ), from v ref to i out2 . offset adjustment 1. adjust v ref to approximately +10v. 2. connect all digital inputs to logic 1. 3. adjust i out2 ampli?er offset adjust trimpot for 0v 1mv at i out2 ampli?er output. 4. connect msb (bit 1) to logic 1 and all other bits to logic 0. 5. adjust i out1 ampli?er offset adjust trimpot for 0v 1mv at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1-2- (n-1) volts reading. (n = 10 for ad7520 and ad7530, and n = 12 for ad7521 and ad7531). 3. to increase v out , connect a series resistor of up to 250 w between v out and r feedback . 4. to decrease v out , connect a series resister of up to 250 w between the reference voltage and the v ref terminal. table 2. blpolar (offset binary) code table digital input analog output 1111111111 -v ref (1-2 -(n-1) ) 1000000001 -v ref (2 -(n-1) ) 1000000000 0 0111111111 v ref (2 -(n-1) ) 0000000001 v ref (1-2 -(n-1) ) 0000000000 v ref notes: 1. lsb = 2 -(n-1) v ref 2. n = 10 for 7520, 7521 n = 12 for 7530,7531 15 16 1 5 4 13 3 2 ad7520 bit 1 bit 10 14 +15v v ref i out2 6 v out - + r feedback 6 - + (msb) (lsb) i out1 r1 10k 0.01% r2 10k 0.01% digital input r3 10m w
8-11 ad7520, ad7530 die characteristics die dimensions: 101 x 103mils (2565 x 2616micrms) metallization: type: pure aluminum thickness: 10 1k ? glassivation: type: psg/nitride psg: 7 1.4k ? nitride: 8 1.2k ? process: cmos metal gate metallization mask layout ad7520, ad7530 pin 3 gnd pin 2 i out 2 pin 1 i out 1 pin 16 r feedback pin 15 v ref pin 14 v+ nc nc pin 12 pin 4 bit 1 (msb) pin 5 bit 2 pin 6 bit 3 pin 7 bit 4 pin 11 bit 8 pin 10 bit 7 pin 9 bit 6 pin 8 bit 5 bit 9 pin 13 bit 10 (lsb)
8-12 ad7521, ad7531 die characteristics die dimensions: 101 x 103mils (2565 x 2616micrms) metallization: type: pure aluminum thickness: 10 1k ? glassivation: type: psg/nitride psg: 7 1.4k ? nitride: 8 1.2k ? process: cmos metal gate metallization mask layout ad7521, ad7531 pin 3 gnd pin 2 i out 2 pin 1 i out 1 pin 18 r feedback pin 17 v ref pin 16 v+ pin 12 pin 4 bit 1 (msb) pin 5 bit 2 pin 6 bit 3 pin 7 bit 4 pin 11 bit 8 pin 10 bit 7 pin 9 bit 6 pin 8 bit 5 bit 9 pin 13 bit 10 pin 14 bit 11 pin 15 bit 12 (lsb)
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